rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a wideband, fast settling op amp AD840 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 connection diagrams features wideband ac performance gain bandwidth product: 400 mhz (gain 3 10) fast settling: 100 ns to 0.01% for a 10 v step slew rate: 400 v/ m s stable at gains of 10 or greater full power bandwidth: 6.4 mhz for 20 v p-p into a 500 v load precision dc performance input offset voltage: 0.3 mv max input offset drift: 3 m v/ 8 c typ input voltage noise: 4 nv/ ? hz open-loop gain: 130 v/mv into a 1 k v load output current: 50 ma min supply current: 12 ma max applications video and pulse amplifiers dac and adc buffers line drivers available in 14-pin plastic dip, hermetic cerdip and 20-pin lcc packages and in chip form mil-std-883b processing available product description the AD840 is a member of the analog devices family of wide bandwidth operational amplifiers. this high speed/high precision family includes, among others, the ad841, which is unity- gain stable, and the ad842, which is stable at a gain of two or greater and has 100 ma minimum output current drive. these devices are fabricated using analog devices junction isolated complementary bipolar (cb) process. this process permits a combination of dc precision and wideband ac performance previously unobtainable in a monolithic op amp. in addition to its 400 mhz gain bandwidth product, the AD840 offers extremely fast settling characteristics, typically settling to within 0.01% of final value in 100 ns for a 10 volt step. the AD840 remains stable over its full operating temperature range at closed-loop gains of 10 or greater. it also offers a low quiescent current of 12 ma maximum, a minimum output current drive capability of 50 ma, a low input voltage noise of 4 nv/ ? hz and a low input offset voltage of 0.3 mv maximum (AD840k). the 400 v/ m s slew rate of the AD840, along with its 400 mhz gain bandwidth, ensures excellent performance in video and pulse amplifier applications. this amplifier is ideally suited for use in high frequency signal conditioning circuits and wide bandwidth active filters. the extremely rapid settling time of the AD840 makes it the preferred choice for data acquisition appli- cations which require 12-bit accuracy. the AD840 is also ap- propriate for other applications such as high speed dac and adc buffer amplifiers and other wide bandwidth circuitry. application highlights 1. the high slew rate and fast settling time of the AD840 make it ideal for dac and adc buffers, line drivers and all types of video instrumentation circuitry. 2. the AD840 is truly a precision amplifier. it offers 12-bit accuracy to 0.01% or better and wide bandwidth, perfor- mance previously available only in hybrids. 3. the AD840s thermally balanced layout and the high speed of the cb process allow the AD840 to settle to 0.01% in 100 ns without the long tails that occur with other fast op amps. 4. laser wafer trimming reduces the input offset voltage to 0.3 mv max on the k grade, thus eliminating the need for external offset nulling in many applications. offset null pins are provided for additional versatility. 5. full differential inputs provide outstanding performance in all standard high frequency op amp applications where circuit gain will be 10 or greater. 6. the AD840 is an enhanced replacement for the ha2540. plastic dip (n) package and cerdip (q) package lcc (e) package
AD840Cspecifications model AD840j AD840k AD840s conditions min typ max min typ max min typ max units input offset voltage 1 0.2 1 0.1 0.3 0.2 1 mv t min Ct max 1.5 0.7 2mv offset drift 5 3 5 m v/ c input bias current 3.5 8 3.5 5 3.5 8 m a t min Ct max 10 6 12 m a input offset current 0.1 0.4 0.1 0.2 0.1 0.4 m a t min Ct max 0.5 0.3 0.6 m a input characteristics differential mode input resistance 30 30 30 k w input capacitance 2 2 2 pf input voltage range common mode 6 10 12 6 10 12 10 12 v common-mode rejection v cm = 10 v 90 110 106 115 90 110 db t min Ct max 85 90 85 db input voltage noise f = 1 khz 4 4 4 nv/ ? hz wideband noise 10 hz to 10 mhz 10 10 10 m v rms open-loop gain v o = 10 v r load = 1 k w 100 130 100 130 100 130 v/mv t min Ct max 50 80 75 100 50 80 v/mv r load = 500 w 75 100 75 v/mv t min Ct max 50 75 50 v/mv output characteristics voltage r load 3 500 w t min Ct max 6 10 6 10 6 10 v current v out = 10 v 50 50 50 ma output resistance open loop 15 15 15 w frequency response gain bandwidth product v out = 90 mv p-p a v = C10 400 400 400 mhz full power bandwidth 2 v o = 20 v p-p r load = 500 w 5.5 6.4 5.5 6.4 5.5 6.4 mhz rise time a v = C10 10 10 10 ns overshoot 3 a v = C10 20 20 20 % slew rate 3 a v = C10 350 400 350 400 350 400 v/ m s settling time 3 C 10 v step a v = C10 to 0.1% 80 80 80 ns to 0.01% 100 100 100 ns overdrive recovery Coverdrive 190 190 190 ns +overdrive 350 350 350 ns differential gain f = 4.4 mhz 0.025 0.025 0.025 % differential phase f = 4.4 mhz 0.04 0.04 0.04 degree power supply rated performance 15 15 15 v operating range 6 5 6 18 6 5 6 18 6 5 6 18 v quiescent current 12 14 12 14 12 14 ma t min Ct max 16 16 18 ma power supply rejection ratio v s = 5 v to 18 v 90 100 94 100 90 100 db t min Ct max 80 86 80 db temperature range rated performance 4 0 +75 0 +75 C55 +125 c transistor count # of transistors 72 72 72 rev. c C2C (@ +25 8 c and 6 15 v dc, unless otherwise noted)
notes 1 input offset voltage specifications are guaranteed after 5 minutes at t a = +25 c. 2 full power bandwidth = slew rate/2 p v peak . 3 refer to figures 22 and 23. 4 s grade t min Ct max specifications are tested with automatic test equipment at t a = C55 c and t a = +125 c. all min and max specifications are guaranteed. specifications shown in boldface are tested on all production units. specifications subject to change without notice. AD840 rev. c C3C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 plastic (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 w cerdip (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 w lcc (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 w input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . 6 v storage temperature range q, e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C65 c to +150 c n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C65 c to +125 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . +175 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 maximum internal power dissipation is specified so that t j does not exceed +175 c at an ambient temperature of +25 c. thermal characteristics: q jc q ja derate at cerdip package 30 c/w 110 c/w 8.7 mw/ c plastic package 30 c/w 100 c/t 10 mw/ c lcc package 35 c/w 150 c/w 6.7 mw/ c recommended heat sink: aavid engineering? #602b ordering guide models package options 2 AD840jn n-14 AD840kn n-14 AD840jq q-14 AD840kq q-14 AD840sq q-14 AD840sq-883b q-14 5962-89640012a q-14 AD840se-883b e-20a 5962-8964001ca e-20a notes 1 j and s grade chips also available. 2 n = plastic dip; q = cerdip; e = lcc (leadless 2 ceramic chip carrier). plastic dip (n) package and cerdip (q) package lcc (e) package AD840 connection diagrams metalization photograph contact factory for latest dimensions. dimensions shown in inches and (mm).
figure 1. input common-mode range vs. supply voltage figure 4. quiescent current vs. supply voltage figure 7. quiescent current vs. temperature AD840Ctypical characteristics rev. c C4C (at +25 8 c and v s = 6 15 v, unless otherwise noted) figure 2. output voltage swing vs. supply voltage figure 5. input bias current vs. temperature figure 8. short-circuit current limit vs. temperature figure 3. output voltage swing vs. load resistance figure 6. output impedance vs. frequency figure 9. gain bandwidth product vs. temperature
AD840 rev. c C5C figure 10. open-loop gain and phase margin phase vs. frequency figure 13. common-mode rejection vs. frequency figure 16. harmonic distortion vs. frequency figure 11. open-loop gain vs. supply voltage figure 14. large signal frequency response figure 17. input voltage noise spectral density figure 12. power supply rejection vs. frequency figure 15. output swing and error vs. settling time figure 18. slew rate vs. temperature
AD840 rev. c C6C figure 19a. inverting amplifier configuration (dip pinout) figure 19c. inverter small signal pulse response figure 19b. inverter large signal pulse response figure 20a. noninverting amplifier configuration (dip pinout) figure 20c. noninverting small signal pulse response figure 20b. noninverting large signal pulse response figure 21. offset nulling (dip pinout) offset nulling the input offset voltage of the AD840 is very low for a high speed op amp, but if additional nulling is required, the circuit shown in figure 21 can be used.
applying the AD840 rev. c C7C figure 24 shows the long-term stability of the settling charac- teristics of the AD840 output after a 10 v step. there is no evi- dence of settling tails after the initial transient recovery time. the use of a junction isolated process, together with careful lay- out, avoids these problems by minimizing the effects of transis- tor isolation capacitance discharge and thermally induced shifts in circuit operating points. these problems do not occur even under high output current conditions. figure 24. AD840 settling demonstrating no settling tails grounding and bypassing in designing practical circuits with the AD840, the user must re- member that whenever high frequencies are involved, some spe- cial precautions are in order. circuits must be built with short interconnect leads. large ground planes should be used when- ever possible to provide a low resistance, low inductance circuit path, as well as minimizing the effects of high frequency cou- pling. sockets should be avoided, because the increased inter-lead capacitance can degrade bandwidth. feedback resistors should be of low enough value to assure that the time constant formed with the circuit capacitances will not limit the amplifier performance. resistor values of less than 5 k w are recommended. if a larger resistor must be used, a small ( 10 pf) feedback capacitor in connected parallel with the feed- back resistor, r f , may be used to compensate for these stray ca- pacitances and optimize the dynamic performance of the amplifier in the particular application. power supply leads should be bypassed to ground as close as possible to the amplifier pins. a 2.2 m f capacitor in parallel with a 0.1 m f ceramic disk capacitor is recommended. capacitive load driving ability like all wideband amplifiers, the AD840 is sensitive to capaci- tive loading. the AD840 is designed to drive capacitive loads of up to 20 pf without degradation of its rated performance. capacitive loads of greater than 20 pf will decrease the dynamic performance of the part although instability should not occur unless the load exceeds 100 pf. a resistor in series with the out- put can be used to decouple larger capacitive loads. using a heat sink the AD840 draws less quiescent power than most high speed amplifiers and is specified for operation without a heat sink. however, when driving low impedance loads the current to the load can be 4 to 5 times the quiescent current. this will create a noticeable temperature rise. improved performance can be achieved by using a small heat sink such as the aavid engineer- ing #602b. AD840 settling time figures 22 and 24 show the settling performance of the AD840 in the test circuit shown in figure 23. settling time is defined as: the interval of time from the application of an ideal step function input until the closed-loop amplifier output has entered and remains within a specified error band. this definition encompasses the major components which com- prise settling time. they include (1) propagation delay through the amplifier; (2) slewing time to approach the final output value; (3) the time of recovery from the overload associated with slewing; and (4) l inear settling to within the specified error band. expressed in these terms, the measurement of settling time is obviously a challenge and needs to be done accurately to assure the user that the amplifier is worth consideration for the application. figure 22. AD840 0.01% settling time tek 7a13 tek 7a18 tek 7603 oscilloscope error amp (x11) ddd5109 flat-top pulse generator 5 4 11 10 6 2.2? 0.1? +15v fet probe tek p6201 499 4.99k 50 AD840 4.99k 0.1? 2.2? 499 499 -15v hp6263 499 w w w w w w w figure 23. settling time test circuit figure 23 shows how measurement of the AD840s 0.01% set- tling in 100 ns was accomplished by amplifying the error signal from a false summing junction with a very high speed propri- etary hybrid error amplifier specially designed to enable testing of small settling errors. the device under test was driving a 420 w load. the input to the error amp is clamped in order to avoid possible problems associated with the overdrive recovery of the oscilloscope input amplifier. the error amp amplifies the error from the false summing junction by 11, and it contains a gain vernier to fine trim the gain.
AD840 rev. c C8C c1176aC5C11/90 printed in u.s.a. high speed dac buffer circuit the AD840s 100 ns settling time to 0.01% for a 10 v step makes it well suited as an output buffer for high speed d/a con- verters. figure 25 shows the connections for producing a 0 to +10.24 v output swing from the ad568 35 ns dac. with the ad568 in unbuffered voltage output mode, the AD840 is placed in noninverting configuration. as a result of the 1 k w span resistor provided internally in the ad568, the noise gain of this topology is 10. only 5 pf is required across the feedback (span) resistor to optimize settling. figure 25. 0 v to +10.24 v dac output buffer overdrive recovery figure 26 shows the overdrive recovery capability of the AD840. typical recovery time is 190 ns from negative overdrive and 350 ns from positive overdrive. figure 26. overdrive recovery figure 27. overdrive recovery test circuit 14-pin plastic (n) package 20-pin lcc (e) package outline dimensions dimensions shown in inches and (mm). 14-pin cerdip (q) package
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